In 1987 he joined the Electrical and Computer Engineering Department of the University of Patras, from which he graduated (five-year diploma degree) in December 1992. His diploma thesis entitled 'VLSI implementation of a square root extractor using digit-serial processing techniques', was carried out at the VLSI Design Laboratory of the department.
From mid 1993 until the end of 1998 he was pursued his Ph.D. thesis entitled 'Analytical timing and power dissipation models for static CMOS circuits'.
The thesis was carried out at the VLSI Design Laboratory of the Electrical and Computer Engineering Department of the University of Patras. Analytical models for the evaluation of the transient response and the energy dissipation (especially the short-circuit part) of the CMOS inverter were developed, which take into account the influences of all circuit parameters, and the effects of submicron devices. In addition, the inverter models were extended to complex CMOS gates in order to achieve accurate and fast simulation of CMOS circuits.
Education
