J1. L. Bisdounis, S. Nikolaidis, O. Koufopavlou, Propagation delay and short-circuit power dissipation modeling of the CMOS inverter, IEEE Transactions on Circuits and Systems - Part I: Fundamental Theory and Applications, vol. 45, no. 3, pp. 259-270, March 1998.
J2. L. Bisdounis, S. Nikolaidis, O. Koufopavlou, Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices, IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 302-306, February 1998.
J3. L. Bisdounis, O. Koufopavlou, Short-circuit energy dissipation modeling for submicrometer CMOS gates, IEEE Transactions on Circuits and Systems - Part I: Fundamental Theory and Applications, vol. 47, no. 9, pp. 1350-1361, September 2000.
J4. L. Bisdounis, S. Nikolaidis, O. Koufopavlou, Analytical model for the CMOS short-circuit power dissipation, Integrated Computer-Aided Engineering Journal, IOS Press, vol. 5, no. 2 (special issue on low-power electronic systems), pp. 129-140, April 1998.
J5. L. Bisdounis, O. Koufopavlou, S. Nikolaidis, Modeling output waveform and propagation delay of a CMOS inverter in the submicron range, IEE Circuits, Devices and Systems, vol. 145, no. 6, pp. 402-408, December 1998.
J6. L. Bisdounis, D. Gouvetas, O. Koufopavlou, A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits, International Journal of Electronics, Taylor & Francis, vol. 84, no. 6, pp. 599-613, June 1998.
J7. L. Bisdounis, G. Panagiotaras, O. Koufopavlou, C. E. Goutis, CMOS multi-input gate implementations for low-power digital design, International Journal of Electronics, Taylor & Francis, vol. 79, no. 5, pp. 641-653, November 1995.
J8. L. Bisdounis, D. E. Metafas, A.M. Maras, C. Mavridis, VLSI implementation of digit-serial arithmetic modules, Microprocessing and Microprogramming Journal, North-Holland (Elsevier), vol. 39, no. 2-5, pp. 251-254, December 1993.
J9. L. Bisdounis, C. Dre, S. Blionas, D. Metafas, A. Tatsaki, F. Ieromnimon, E. Macii, Ph. Rouzet, R. Zafalon, L. Benini, Low-power system-on-chip architecture for wireless LANs, IEE Computers and Digital Techniques, vol. 151, no. 1, pp. 2-15, January 2004.
J10. C. Drosos, L. Bisdounis, D. Metafas, S. Blionas, A. Tatsaki, G. Papadopoulos, Hardware-software design and validation framework for wireless LAN modems, IEE Computers and Digital Techniques, vol. 151, no. 3, pp. 173-182, May 2004.
J11. S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas, Instruction-level energy modeling for pipelined processors, Journal of Embedded Computing, IOS Press, vol. 1, no. 3 (special issue on low-power embedded systems), pp. 317-324, March 2006.
J12. L. Bisdounis, S. Blionas, E. Macii, S. Nikolaidis, R. Zafalon, Implementation strategy and results of an energy-aware system-on-chip for 5GHz WLAN applications, Journal of Low-Power Electronics, American Scientific Publishers, vol. 2, no. 1, pp. 18-26, April 2006.
J13. L. Bisdounis, Analytical modeling of overshooting effect in sub-100nm CMOS inverters, Journal of Circuits, Systems, and Computers, World Scientific, vol. 20, no. 7, pp. 1303-1321, November 2011.
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